A New Type of RAM Proposed That Will Accelerate The Development of Artificial Intelligence

Solving tasks using artificial intelligence is accompanied by processing huge amounts of data, which almost always exceeds the cache memory capabilities of processors. Therefore, the ideal memory for AI would be inside the processor and with high power efficiency. Such memory was proposed separately by researchers from the U.S. and Belgium.

Capacitorless memory cell (orange — tungsten-doped indium oxide, yellow — palladium transistor gate, green — nickel drain and source electrodes, blue — hafnium oxide dielectric). Image source: University of Notre Dam

As you know, the classic RAM DRAM is a circuit of one control transistor and a capacitor (1T1C), which stores the charge, then the cell is written 1 or discharged, which means 0. The energy consumption goes both for data recording and reading (when reading the capacitor loses some capacity and it must be replenished), and also for data regeneration in all cells with a frequency of about once every 64 ms. Researchers at the University of Notre Dame in the U.S. proposed to solve the issue at the root and presented a DRAM cell without a capacitor, but with two transistors — 2T0C.

The idea is that the gate transistor is a small capacitor. Then one transistor in the circuit plays the role of the control transistor (the left one in the diagram below) and the second one stores the charge (information). In addition, in the proposed circuit both transistors work independently, one of which writes data and the second performs reading. For example, if the gate of the second transistor contains a charge, it is open and a current flows through it, which can be “read”.

The problem with the implementation of the proposed scheme is exactly one thing — not to let the self-discharge in the gate of the “memory” transistor. Therefore, researchers select semiconductor materials that minimize leakage currents and currents through the transistors in the closed state.

Conventional silicon is not good for this. At the University of Notre Dame, for example, a prototype 2T0C cell was made using indium oxide doped with up to 1% tungsten (IWO). It is claimed that the resulting circuit has two to three orders of magnitude less leakage currents than silicon.

Researchers from the Belgian Imec center used other materials in the 2T0C circuit, namely the IGZO (indium gallium-zinc oxide) combination already known from Sharp displays. However, the classic processes using IGZO were not suitable for manufacturing 2T0C memory, and they had to be significantly refined. But Imec memory turned out to be close to non-volatile.

The Belgian 2T0C cell had an average data hold time of 200 seconds, and 25% of cells held a charge over 400 seconds, thousands of times longer than conventional DRAM cells. Moreover, Imec expects to be able to extend the data retention time of 2T0C cells without regeneration to 100 hours or more.

Schematic diagram of a 2T0C memory cell. Image source: University of Notre Dam

Finally, 2T0C memory cells, because they do not have quite large capacitors, can be made in or above the processor’s working layers. This means that it will be possible to endow the processor with so much memory that all the data for the operation will be able to fit into the memory as part of the processor. It won’t be a cache, but it will still be much closer (and faster in terms of access) to the processor logic than DRAM modules.

All combined, this could take AI algorithm execution to new and unreachable heights today. Ordinary computers could be transformed, too.

All that remains is to wait.